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J. Marques-Silva and T. Glass, “Combinational equivalence checking using satisfiability and recursive learning,” IEEE/ACM Design, Automation and Test in Europe, pp. 145–149, 1999.

**J. Marques‑Silva and T. Glass, “Combinational equivalence checking using satisfiability and recursive learning,” IEEE/ACM Design, Automation and Test in Europe, pp. 145–149, 1999.**

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When the world of digital design was still wrestling with the exponential growth of transistor counts, two researchers—João Marques‑Silva and Tom Glass—published a landmark paper that would change the way engineers approach **combinational equivalence checking (CEC)**. Their 1999 article, *“Combinational equivalence checking using satisfiability and recursive learning,”* introduced a novel blend of **SAT‑based solving** and **recursive learning** that quickly became a cornerstone of modern **hardware verification**. In this post we’ll unpack the key ideas behind the paper, explore why it matters today, and highlight how its concepts continue to power the most advanced **formal verification** tools.

### The Problem: Verifying Logic Equivalence at Scale

In digital design, *combinational equivalence checking* ensures that two representations of a circuit—often a high‑level behavioral model and its optimized gate‑level netlist—produce identical outputs for every possible input combination. Traditional methods relied on binary decision diagrams (BDDs) or exhaustive simulation. While effective for small designs, these techniques falter as the number of inputs climbs into the hundreds or thousands, leading to **state‑space explosion** and prohibitive runtimes.

### The SAT Revolution

The late 1990s saw the rise of **satisfiability (SAT) solvers**—algorithms capable of determining whether a Boolean formula can be satisfied. SAT offered a linear‑space alternative to BDDs, but early attempts to apply SAT directly to CEC suffered from poor scalability because they treated the equivalence problem as a monolithic SAT instance.

Marques‑Silva and Glass turned this limitation into an opportunity. Their core insight was to **decompose the equivalence problem** into a series of smaller SAT queries, each focusing on a localized portion of the circuit. By iteratively learning from each SAT result—hence the term *recursive learning*—the algorithm could prune irrelevant search space and converge on a proof of equivalence (or a counterexample) far more efficiently.

### Recursive Learning in Action

1. **Partitioning the Circuit** – The design is split into manageable sub‑circuits. Each sub‑circuit is encoded as a set of Boolean clauses.
2. **Local SAT Queries** – A SAT solver checks whether the outputs of a pair of corresponding sub‑circuits can differ. If the solver returns UNSAT, the sub‑circuits are proven equivalent.
3. **Clause Learning** – When the solver discovers a conflict (i.e., a potential mismatch), it generates a learned clause that captures the root cause of the conflict. This clause is fed back into the global verification context.
4. **Recursive Propagation** – Learned clauses are reused across subsequent sub‑circuits, enabling the solver to avoid re‑exploring previously ruled‑out assignments. The process repeats until all partitions are verified or a genuine counterexample emerges.

The elegance of this approach lies in its **feedback loop**: each SAT call not only answers a local question but also enriches the knowledge base for the entire verification task.

### Impact on Modern Verification Tools

Fast forward two decades, and the principles introduced by Marques‑Silva and Glass are embedded in leading EDA (Electronic Design Automation) suites:

– **Formal equivalence checking (FEC)** engines now routinely combine SAT, **SMT (Satisfiability Modulo Theories)**, and recursive learning to handle designs with billions of gates.
– **Incremental SAT solving**—a direct descendant of recursive learning—allows tools to retain solver state across multiple queries, dramatically reducing runtime for iterative design flows.
– **Hybrid verification** strategies blend simulation, BDDs, and SAT, leveraging the strengths of each technique while mitigating weaknesses.

Because the paper demonstrated that *SAT‑based CEC could scale to realistic industrial designs*, it spurred a wave of research into **conflict‑driven clause learning (CDCL)**, **interpolant generation**, and **proof‑logging**, all of which are now standard in formal verification.

### Why the 1999 Publication Still Matters

– **Academic relevance** – The paper is frequently cited in conferences such as **DAC**, **DATE**, and **ICCAD**, serving as a foundational reference for graduate courses on formal methods.
– **Industry adoption** – Companies like Synopsys, Cadence, and Siemens EDA have built commercial products that trace their algorithmic roots back to the recursive learning framework.
– **Future research** – Emerging topics like **machine‑learning‑guided SAT** and **quantum‑accelerated verification** often benchmark against the original SAT‑recursive learning baseline.

### Takeaways for Designers and Engineers

1. **Leverage SAT‑based CEC** early in the design cycle to catch functional bugs before silicon fabrication.
2. **Embrace incremental verification**—re‑run checks only on changed portions of the netlist to maximize productivity.
3. **Stay updated on solver technologies**; modern SAT solvers incorporate sophisticated heuristics that build directly on the recursive learning concept.

In summary, the 1999 work of Marques‑Silva and Glass did more than solve a specific verification problem—it introduced a paradigm shift that continues to empower **digital design verification**, **ASIC/FPGA development**, and **formal methods research**. Whether you are a seasoned verification engineer or a student exploring the field, understanding the legacy of *“Combinational equivalence checking using satisfiability and recursive learning”* is essential for navigating today’s increasingly complex hardware landscape.