Welcome, visitor! [ Login

 

Haykin, S. (2000) Neural Network a comprehensive foundation. 2nd edition, Prentice Hall.

  • Listed: 29 July 2026 15 h 44 min

Description

Haykin, S. (2000) Neural Network a comprehensive foundation. 2nd edition, Prentice Hall.

None

No Tags

9 total views, 2 today

  

Listing ID: N/A

Report problem

Processing your request, Please wait....

Sponsored Links

 

C. Meinel and H. Sack, “Improving XOR-Node placement for ?-OBDDs,” 5th Inte...

C. Meinel and H. Sack, “Improving XOR-Node placement for ?-OBDDs,” 5th International Workshop on Applications of the Reed-Muller Expansion in Circuit Design, Starkville, Mississippi, USA, […]

1 total views, 1 today

 

M. Fujita, H. Fujisawa, and Y. Matsunaga, “Variable ordering algorithms for...

M. Fujita, H. Fujisawa, and Y. Matsunaga, “Variable ordering algorithms for ordered binary decision diagrams and their evaluation,” IEEE Transactions on CAD, Vol. 12, No. […]

No views yet

 

C. S. Yeh, I. S. Reed, and T. K. Truong, “Systolic multipliers for finite f...

C. S. Yeh, I. S. Reed, and T. K. Truong, “Systolic multipliers for finite fields GF(2m),” IEEE Transactions on Computers, Vol. 33, No. 4, pp. […]

No views yet

 

K. M. Butler, D. E. Ross, R. Kapur, and M. R. Mercer, “Heuristics to comput...

K. M. Butler, D. E. Ross, R. Kapur, and M. R. Mercer, “Heuristics to compute variable orderings for efficient manipulation of ordered binary decision diagrams,” […]

1 total views, 1 today

 

K. S. Brace, R. L. Rudell, and R. E. Bryant, “Efficient implementation of a...

K. S. Brace, R. L. Rudell, and R. E. Bryant, “Efficient implementation of a BDD package,” 27th ACM/IEEE Design Automation Conference, pp. 40–45, 1990. “K. […]

1 total views, 1 today

 

F. Somenzi, “CUDD: CU decision diagram package,” Uni- versity of Colorado a...

F. Somenzi, “CUDD: CU decision diagram package,” Uni- versity of Colorado at Boulder. http://vlsi.colorado. edu/ ~ fabio/CUDD/. Here’s a thinking process: 1. **Analyze User Input:** […]

No views yet

 

C. Meinel and H. Sack, “?-OBDDs–A BDD structure for probabilistic verificat...

C. Meinel and H. Sack, “?-OBDDs–A BDD structure for probabilistic verification,” Pre-LICS Workshop on Probabilistic Methods in Verification (PROBMIV’98), Indianapolis, IN, USA, pp. 141–151, 1998. […]

1 total views, 1 today

 

P. A. Scott, S. E. Tavares, and L. E. Peppard, “A fast VLSI multiplier for ...

P. A. Scott, S. E. Tavares, and L. E. Peppard, “A fast VLSI multiplier for GF(2m),” IEEE Journal on Selected Areas in Communications, Vol. 4, […]

No views yet

 

J. C. Madre and J. P. Billón, “Proving Circuit correctness using formal com...

J. C. Madre and J. P. Billón, “Proving Circuit correctness using formal comparison between expected and extracted behaviour,” Proceedings of 25th ACM/IEEE Design Automation Conference, […]

No views yet

 

R. Lidl and H. Niederreiter, “Finite fields,” Addison-Wesley, Reading, MA, ...

R. Lidl and H. Niederreiter, “Finite fields,” Addison-Wesley, Reading, MA, 1983. **R. Lidl and H. Niederreiter, “Finite fields,” Addison-Wesley, Reading, MA, 1983.** The 1983 classic […]

No views yet

 

C. Meinel and H. Sack, “Improving XOR-Node placement for ?-OBDDs,” 5th Inte...

C. Meinel and H. Sack, “Improving XOR-Node placement for ?-OBDDs,” 5th International Workshop on Applications of the Reed-Muller Expansion in Circuit Design, Starkville, Mississippi, USA, […]

1 total views, 1 today

 

M. Fujita, H. Fujisawa, and Y. Matsunaga, “Variable ordering algorithms for...

M. Fujita, H. Fujisawa, and Y. Matsunaga, “Variable ordering algorithms for ordered binary decision diagrams and their evaluation,” IEEE Transactions on CAD, Vol. 12, No. […]

No views yet

 

C. S. Yeh, I. S. Reed, and T. K. Truong, “Systolic multipliers for finite f...

C. S. Yeh, I. S. Reed, and T. K. Truong, “Systolic multipliers for finite fields GF(2m),” IEEE Transactions on Computers, Vol. 33, No. 4, pp. […]

No views yet

 

K. M. Butler, D. E. Ross, R. Kapur, and M. R. Mercer, “Heuristics to comput...

K. M. Butler, D. E. Ross, R. Kapur, and M. R. Mercer, “Heuristics to compute variable orderings for efficient manipulation of ordered binary decision diagrams,” […]

1 total views, 1 today

 

K. S. Brace, R. L. Rudell, and R. E. Bryant, “Efficient implementation of a...

K. S. Brace, R. L. Rudell, and R. E. Bryant, “Efficient implementation of a BDD package,” 27th ACM/IEEE Design Automation Conference, pp. 40–45, 1990. “K. […]

1 total views, 1 today

 

F. Somenzi, “CUDD: CU decision diagram package,” Uni- versity of Colorado a...

F. Somenzi, “CUDD: CU decision diagram package,” Uni- versity of Colorado at Boulder. http://vlsi.colorado. edu/ ~ fabio/CUDD/. Here’s a thinking process: 1. **Analyze User Input:** […]

No views yet

 

C. Meinel and H. Sack, “?-OBDDs–A BDD structure for probabilistic verificat...

C. Meinel and H. Sack, “?-OBDDs–A BDD structure for probabilistic verification,” Pre-LICS Workshop on Probabilistic Methods in Verification (PROBMIV’98), Indianapolis, IN, USA, pp. 141–151, 1998. […]

1 total views, 1 today

 

P. A. Scott, S. E. Tavares, and L. E. Peppard, “A fast VLSI multiplier for ...

P. A. Scott, S. E. Tavares, and L. E. Peppard, “A fast VLSI multiplier for GF(2m),” IEEE Journal on Selected Areas in Communications, Vol. 4, […]

No views yet

 

J. C. Madre and J. P. Billón, “Proving Circuit correctness using formal com...

J. C. Madre and J. P. Billón, “Proving Circuit correctness using formal comparison between expected and extracted behaviour,” Proceedings of 25th ACM/IEEE Design Automation Conference, […]

No views yet

 

R. Lidl and H. Niederreiter, “Finite fields,” Addison-Wesley, Reading, MA, ...

R. Lidl and H. Niederreiter, “Finite fields,” Addison-Wesley, Reading, MA, 1983. **R. Lidl and H. Niederreiter, “Finite fields,” Addison-Wesley, Reading, MA, 1983.** The 1983 classic […]

No views yet